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PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:2.0
BEGIN:VEVENT
DTSTART:20151117T231500Z
DTEND:20151118T010000Z
LOCATION:Level 4 - Lobby
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: In this paper, we present a cost effective FPGA based data plane design which reuses existing I/O devices such as 10GbE NICs or NVM-e SSDs as data ingress and egress ports.  We achieved this by building a FPGA based device driver  logic which is capable of exploiting PCI-e point to point communication.  FPGA H/W design support such as C based High Level Synthesis tools enabled us to implement complex device drivers within FPGAs.  Our design avoids re-implementing the performance and stability of existing ASIC based commodity I/O devices, already installed in our systems, thus reducing data plane implementation costs.
SUMMARY:Cost Effective Programmable H/W Based Data Plane Acceleration: Linking PCI-Express Commodity I/O H/W with FPGAs
PRIORITY:3
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