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PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
BEGIN:VEVENT
DTSTART:20151116T193000Z
DTEND:20151116T230000Z
LOCATION:15
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: With the recent announcement of AVX-512, the biggest extension to Intel Instruction Set Architecture (ISA), the next generation of Intel’s multicore and many-core product lines will be built around its features such as wider SIMD ALU, more vector registers, new masking architecture for prediction, embedded broadcast and rounding capabilities and the new integer/floating-point instructions. AVX-512 ushers in a new era of converged ISA computing in which the HPC application developer needs to utilize these hardware features through programming tools for maximum performance.  =0AThis tutorial is the first to bring the AVX-512 ISA to the Supercomputing Community. The first part covers AVX-512 architecture, design philosophy, key features and its performance characteristics.   The second part covers the programming tools such as compilers, libraries and the profilers that support the new ISA in a parallel programming framework to guide the developers step-by-step to turn their scalar serial applications into vector parallel applications. Central to the second part is the explicit vector programming methodology under the new industry standard, OpenMP* 4.0 and 4.1.  We will present many examples that illustrate how the power of the compiler can be harnessed with minimal user effort to enable SIMD parallelism with AVX-512 instructions from high-level language constructs.
SUMMARY:Getting Started with Vector Programming using AVX-512 on Multicore and Many-Core Platforms
PRIORITY:3
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