SCHEDULE: NOV 15-20, 2015

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Reinstating Moore’s Law with Transistor-Level 3D Using Foundry Wafers and Depreciated Process Nodes

SESSION: Hardware and Architecture

EVENT TYPE: Exhibits, Exhibitor Forums

EVENT TAG(S): Hardware and Architecture

TIME: 4:30PM - 5:00PM

SESSION CHAIR(S): David Martin

Presenter(s):David Chapman

ROOM:12AB

ABSTRACT:

More than a decade of 3D packaging efforts have yielded marginal, but sorely needed performance improvements. Yet those efforts have done nothing directly to address the demise of transistor density improvements, the undoing of Moore’s Law. Even using mature process nodes, transistor-scale 3D introduced by Tezzaron at SC15, allows transistor densities that exceed any anticipated at even 7 nm, the broadly acknowledged “end of silicon”. Interconnect parasitics, which have become the primary source of delays and power consumption, can easily be reduced by factors of 10 to 1000. Transistor-scale 3D applied to memory produces dramatic reductions in latency and power and allows vastly improved transaction rates, key to many HPC applications; and can be expected to produce similar results when applied to the design and fabrication of processors and other complex ICs, allowing cost effective extension of Moore’s law in conventional CMOS for another one or two decades.

Chair/Presenter Details:

David Martin (Chair) - Argonne National Laboratory|

David Chapman - Tezzaron

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