sponsored byACMIEEE The International Conference for High Performance 
Computing, Networking, Storage and Analysis
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SCHEDULE: NOV 15-20, 2015

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Programming Models for Parallel Architectures and Requirements for Pre-Exascale

SESSION: Programming Models for Parallel Architectures and Requirements for Pre-Exascale


EVENT TAG(S): Performance, HPC Futures and Exascale, Hardware and Architecture, Software for HPC

TIME: 3:30PM - 5:00PM

Panelists:Fernanda Foertter, Barbara Chapman, Steve Oberlin, Satoshi Matsuoka, Jack Wells, Si Hammond



Relying on domain scientists to provide programmer intervention to develop applications to emerging exascale platforms is a real challenge. A scientist prefers to express mathematics of the science, not describe the parallelism of the implementing algorithms. Do we expect too much of the scientist to code for high parallel performance given the immense capabilities of the platform. This ignores that the scientist may have a mandate to code for a new architecture, and yet preserve portability in their code. This panel will bring together user experience, programming model, architecture experts to discuss the pressing needs in finding the path forward to port scientific codes to such a platform. We hope to discuss the evolving programming stack, application-level requirements, and address the hierarchical nature of large systems in terms of different cores, memory levels, power consumption and the pragmatic advances of near term technology.

Moderator/Panelist Details:

Fernanda Foertter (Moderator) - Oak Ridge National Laboratory

Barbara Chapman - University of Houston

Steve Oberlin - NVIDIA Corporation

Satoshi Matsuoka - Tokyo Institute of Technology

Jack Wells - Oak Ridge National Laboratory

Si Hammond - Sandia National Laboratories

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