sponsored byACMIEEE The International Conference for High Performance 
Computing, Networking, Storage and Analysis
FacebookTwitterGoogle PlusLinkedInYouTubeFlickr

SCHEDULE: NOV 15-20, 2015

When viewing the Technical Program schedule, on the far righthand side is a column labeled "PLANNER." Use this planner to build your own schedule. Once you select an event and want to add it to your personal schedule, just click on the calendar icon of your choice (outlook calendar, ical calendar or google calendar) and that event will be stored there. As you select events in this manner, you will have your own schedule to guide you through the week.

Parallelization of Tsunami Simulation on CPU, GPU and FPGAs

SESSION: Regular & ACM Student Research Competition Poster Reception

EVENT TYPE: Posters, Receptions, ACM Student Research Competition

EVENT TAG(S): HPC Beginner Friendly, Regular Poster

TIME: 5:15PM - 7:00PM

SESSION CHAIR(S): Michela Becchi, Manish Parashar, Dorian C. Arnold

AUTHOR(S):Fumiya Kono, Naohito Nakasato, Kensaku Hayashi, Alexander Vazhenin, Stanislav Sedukhin, Kohei Nagasu, Kentaro Sano, Vasily Titov

ROOM:Level 4 - Lobby

ABSTRACT:

Tsunami is known as one of serious disasters. MOST (Method of Splitting Tsunami) is one of numerical solvers for modeling tsunami waves. Prediction of the arrival time of Tsunami is critical to evacuate people from coastal area. Therefore, fast computation of MOST enabled by parallel processing is important. We have developed a tsunami propagation code based on MOST and implemented different algorithms for parallelization by OpenMP and OpenACC. We have conducted benchmarking of these parallelized codes on various architectures such as multi-core CPU systems, Many Integrated Core architecture, GPU. In this poster, we compare the performance of various parallel implementations. We found that a parallelized code applied spatial blocking on OpenACC was the best performance at present.
Concurrently, we are developing an accelerator of the MOST computation with Field-Programmable Gate Arrays (FPGAs) for high-performance and power-efficient simulation. We also present preliminary evaluation of its prototype implementation with a 28nm FPGA.

Chair/Author Details:

Michela Becchi, Manish Parashar, Dorian C. Arnold (Chair) - University of Missouri|Rutgers University|University of New Mexico|

Fumiya Kono - University of Aizu

Naohito Nakasato - University of Aizu

Kensaku Hayashi - University of Aizu

Alexander Vazhenin - University of Aizu

Stanislav Sedukhin - University of Aizu

Kohei Nagasu - Tohoku University

Kentaro Sano - Tohoku University

Vasily Titov - National Oceanic and Atmospheric Administration

Add to iCal  Click here to download .ics calendar file

Add to Outlook  Click here to download .vcs calendar file

Add to Google Calendarss  Click here to add event to your Google Calendar