sponsored byACMIEEE The International Conference for High Performance 
Computing, Networking, Storage and Analysis
FacebookTwitterGoogle PlusLinkedInYouTubeFlickr

SCHEDULE: NOV 15-20, 2015

When viewing the Technical Program schedule, on the far righthand side is a column labeled "PLANNER." Use this planner to build your own schedule. Once you select an event and want to add it to your personal schedule, just click on the calendar icon of your choice (outlook calendar, ical calendar or google calendar) and that event will be stored there. As you select events in this manner, you will have your own schedule to guide you through the week.

Programming the Xeon Phi

SESSION: Programming the Xeon Phi

EVENT TYPE: Tutorials

EVENT TAG(S): Programming Systems, Accelerators

TIME: 8:30AM - 5:00PM

Presenter(s):Jerome Vienne, Victor Eijkhout, Kent Milfeld, Si Liu



The Intel Xeon Phi co-processor also known as the MIC is becoming more popular in HPC. Current HPC clusters like Tianhe-2, Stampede and Cascade are currently using this technology, and upcoming clusters like Cori and the Stampede upgrade will be comprised of the next generation of MIC known as the Knights Landing (KNL). However, the MIC architecture has significant features that are different from that of current x86 CPUs. It is important for developers to know these differences to attain optimal performance.
This tutorial is designed to introduce attendees to the MIC architecture in a practical manner and to prepare them for the new generation of the co-processor (KNL). Experienced C/C++ and Fortran programmers will be introduced to techniques essential for utilizing the MIC architecture efficiently. Multiple lectures and exercises will be used to acquaint attendees with the MIC platform and to explore the different execution modes as well as parallelization and optimization through example testing and reports. All exercises will be executed on the Stampede system at the Texas Advanced Computing Center (TACC). Stampede features more than 2PF of performance using 100,000 Intel Xeon E5 cores and an additional 7+ PF of performance from more than 6,400 Xeon Phi.

Chair/Presenter Details:

Jerome Vienne - The University of Texas at Austin

Victor Eijkhout - The University of Texas at Austin

Kent Milfeld - The University of Texas at Austin

Si Liu - The University of Texas at Austin

Add to iCal  Click here to download .ics calendar file

Add to Outlook  Click here to download .vcs calendar file

Add to Google Calendarss  Click here to add event to your Google Calendar