sponsored byACMIEEE The International Conference for High Performance 
Computing, Networking, Storage and Analysis
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SCHEDULE: NOV 15-20, 2015

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How to Analyze the Performance of Parallel Codes 101

SESSION: How to Analyze the Performance of Parallel Codes 101

EVENT TYPE: Tutorials

EVENT TAG(S): Performance, HPC Beginner Friendly

TIME: 8:30AM - 5:00PM

Presenter(s):Martin Schulz, Jim Galarowicz, Don Maghrak, Mahesh Rajan

ROOM:19A

ABSTRACT:

Performance analysis is an essential step in the development of HPC codes. It will even gain in importance with the rising complexity of machines and applications that we are seeing today. Many tools exist to help with this analysis, but the user is too often left alone with interpreting the results.

We will provide a practical road map for the performance analysis of HPC codes and will provide users step by step advice on how to detect and optimize common performance problems, covering both on-node performance and communication optimization as well as issues on threaded and accelerator-based architectures. Throughout this tutorial, we will show live demos using Open|SpeedShop, a comprehensive and easy to use tool set. Additionally, we will provide hands-on exercises for attendees to try out the new techniques learned. All techniques will, however, apply broadly to any tool and we will point out alternative tools where useful.

Chair/Presenter Details:

Martin Schulz - Lawrence Livermore National Laboratory

Jim Galarowicz - Krell Institute

Don Maghrak - Krell Institute

Mahesh Rajan - Sandia National Laboratories

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