Evaluating DVFS and Concurrency Throttling on IBM's Power8 Architecture
Authors: Wei Wang (University of Delaware), Edgar A. Leon (Lawrence Livermore National Laboratory)
Abstract: Two of the world’s next-generation of supercomputers at the U.S. national laboratories will be based on IBM’s Power architecture. Early insights of how this architecture impacts applications are beneficial to attain the best performance. In this work, we investigate the effects of DVFS and thread concurrency throttling on the performance of applications for an IBM OpenPower, Power8 system. We apply these techniques dynamically on a per region basis to three HPC codes: miniFE, LULESH, and Graph500. Our empirical results offer the following insights. First, concurrency throttling provides significant performance improvements. Second, 4-way simultaneous multi-threading (SMT) performs as well as 8-way SMT with potential gains in power-efficiency. And, third, applying informed frequency and concurrency throttling combinations on memory-bound regions results in greater performance and energy efficiency.
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