SCHEDULE: NOV 15-20, 2015

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ENTIRE WEEK SUNDAY MONDAY TUESDAY WEDNESDAY THURSDAY FRIDAY

Cost Effective Programmable H/W Based Data Plane Acceleration: Linking PCI-Express Commodity I/O H/W with FPGAs

SESSION: Regular & ACM Student Research Competition Poster Reception

EVENT TYPE: Posters, Receptions, ACM Student Research Competition

EVENT TAG(S): HPC Beginner Friendly, Regular Poster

TIME: 5:15PM - 7:00PM

SESSION CHAIR(S): Michela Becchi, Manish Parashar, Dorian C. Arnold

AUTHOR(S):Woong Shin, Heon Y. Yeom

ROOM:Level 4 - Lobby

ABSTRACT:

In this paper, we present a cost effective FPGA based data plane design which reuses existing I/O devices such as 10GbE NICs or NVM-e SSDs as data ingress and egress ports. We achieved this by building a FPGA based device driver logic which is capable of exploiting PCI-e point to point communication. FPGA H/W design support such as C based High Level Synthesis tools enabled us to implement complex device drivers within FPGAs. Our design avoids re-implementing the performance and stability of existing ASIC based commodity I/O devices, already installed in our systems, thus reducing data plane implementation costs.

Chair/Author Details:

Michela Becchi, Manish Parashar, Dorian C. Arnold (Chair) - University of Missouri|Rutgers University|University of New Mexico|